Staggered memory cell array
US7327591B2 · kind B2 · utility
94Cited by
3References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2004 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Jun 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
Abstract
A method of placing a cell in an array is disclosed. The method includes placing the cell a plurality of times (600, 602, 604) in a first array. The cell is also placed a plurality of times (606, 608, 610) in a second array. The second array is placed adjacent and offset from the first array by an offset distance (O2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.