Communication protocol processor having multiple microprocessor cores connected in series and dynamically reprogrammed during operation via instructions transmitted along the same data paths used to convey communication data
US7328270B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1999 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Aug 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A communication protocol processor is presented including a transmit unit and a receive unit, each having multiple microprocessor cores connected in series. Each microprocessor core performs an operation upon a stream of communication data, conducted along a data path, according to instructions and associated data stored within a code memory unit. A change in the operation performed by a given microprocessor core is effectuated during communication protocol processor operation by transmitting new instructions and associated data to the microprocessor core along the data path. The new instructions and data modify the existing instructions and associated data stored within the code memory unit. The transmit unit of the communication protocol processor receives packet (i.e., transmit) data in parallel units and produces a framed serial transmit data stream. Each microprocessor core of the transmit unit is assigned one or more tasks which must be accomplished in sequence in order to encapsulate the transmit data stream into frames in accordance with a selected communication protocol. The receive unit receives a framed serial receive data stream and produces packet (i.e., receive) data …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.