Cyclic redundancy check generating circuit
US7328396B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 2004 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Nov 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6572
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit, a method, and a method of designing the circuit, the circuit including: multiple W-bit packet data slice latches; a data partition comprising multiple data XOR subtree levels and having data latches between the data XOR subtree levels; a remainder partition comprising multiple remainder XOR subtree levels and having remainder latches between the remainder XOR subtree levels; a combinatorial XOR tree, outputs of the remainder partition and outputs of the data partition connected to inputs of the combinatorial XOR tree; and a remainder latch, combinatorial XOR tree connected to the remainder latch and the outputs of the remainder latch connected to the remainder partition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.