Solder bumps in flip-chip technologies
US7329951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2005 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Jul 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conducting bond pad in the reference direction, wherein the patterned support/interface layer comprises a hole and a trench, wherein the hole is directly above the electrically conducting bond pad, and wherein the trench is not filled by any electrically conducting material; and (d) an electrically conducting solder bump filling the hole and electrically coupled to the electrically conducting bond pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.