Method of fabricating a semiconductor device
US7329952B2 · kind B2 · utility
2Cited by
2References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2004 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Dec 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor device comprises a copper interconnection 26b buried in an insulating film 16, and a dummy pattern for chemical mechanical polishing buried in the insulating film 16 near the copper interconnection 26b. The unit patterns 26c of the dummy pattern are formed in the density of 10-25%. Even in the case that the electrolytic plating solution for bottom up growth mechanism is used, the step on the surface of a copper film due to over-plating can be decreased, and the total plating thickness necessary to fill the interconnection trenches can be decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.