Use of MTRR and page attribute table to support multiple byte order formats in a computer system
US7330959B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 23, 2004 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | May 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer technology supports multiple byte order formats, separately or simultaneously. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. The PAT has a plurality of entries. Each entry indicates a memory type and a byte order format for a physical address, wherein a plurality of attribute bits and a virtual address are associated with the physical address. A portion of the attribute bits are utilized to select one of the entries. In another embodiment, a memory type range register (MTRR), which is programmable, is utilized to indicate byte order format. The MTRR is configured to indicate a memory type and a byte order format for a range of physical addresses, wherein the memory type and range register (MTRR) receives a physical address and provides a corresponding memory type and a corresponding byte order format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.