Slew rate control mechanism
US7330993B2 · kind B2 · utility
2Cited by
16References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2003 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Nov 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate based upon the state of the signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.