Method of manufacturing a phase change RAM device utilizing reduced phase change current
US7332370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2005 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Aug 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
Abstract
To effectively lower the current required for changing a phase of a phase change layer in a phase change RAM device, metal pads are formed on a semiconductor substrate, and an oxide layer is formed on the metal pads. Nano-sized copolymer patterns aligned with the metal pads covered by the oxide layer are formed on the oxide layer. The oxide layer is etched to form oxide layer patterns by using the nano-sized copolymer patterns as barrier. The nano-sized copolymer patterns are then removed. A nitride layer is deposited and then etched to expose the oxide layer patterns. The exposed oxide layer patterns are removed to form nano-sized holes exposing the metal pads. Bottom electrodes are then formed in the nano-sized holes. A phase change layer and a top electrode are formed on each of the bottom electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.