Method and apparatus for a semiconductor device with a high-k gate dielectric
US7332407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2007 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Apr 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process and apparatus for a high-k gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extend beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.