Silicide structure for ultra-shallow junction for MOS devices
US7332435B2 · kind B2 · utility
2Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2005 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Mar 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.