Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers
US7332929B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2006 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Sep 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system chip has many local blocks including processor cores, caches, and memory controllers. Each local block has a local sample-select mux that is controlled by a local selection control register. The mux selects from among hundreds of internal sample nodes in the local block, and can also pass through samples output by an upstream local block. The selected samples from local blocks are sent to a central on-chip logic analyzer that compares the samples to a maskable trigger value. When the trigger value is matched, a trigger state machine advances, and samples are stored into a central capture buffer. A user debugging the chip can later read out the central capture buffer at a slower speed. Thousands of internal nodes from local blocks can be selected for sampling, triggering, and debugging. Local blocks include valid bits in 64-bit-wide samples. Only valid samples are written to the capture buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.