Dynamic logic with adaptive keeper
US7332937B2 · kind B2 · utility
22Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2005 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Dec 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.