Method and apparatus for distorting duty cycle of a clock
US7332947B2 · kind B2 · utility
3Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2005 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Sep 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for controllably distorting the duty cycle of a clock signal is disclosed. Methods and systems using embodiments of the invention are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.