SRAM memory device with flash clear and corresponding flash clear method
US7333380B2 · kind B2 · utility
4Cited by
9References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Aug 12, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static memory device includes at least one memory cell with two cross-coupled CMOS inverters to be connected to first and second voltages. The substrate of the NMOS transistor of a first CMOS inverter is electrically insulated from the substrate of the NMOS transistor of the second CMOS inverter. The two substrates can be biased with the first voltage. A clear flash controller flash clears the cells for temporarily bring the bias of the substrate of the NMOS transistor of the first CMOS inverter to the second voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.