Optimized FFT/IFFT module
US7333422B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2003 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Mar 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2651
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an optimal hardware implementation of the FFT/IFFT operation that minimizes the number of clock cycles required to compute the FFT/IFFT while at the same time minimizing the number of complex multipliers needed. For performing an N-point FFT/IFFT operation in N clock cycles, the optimal hardware implementation consists of several modules. An input module receives a plurality of inputs in parallel and combines the inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator is used to provide multiplicands to the system. At least two complex multiplier modules for performing complex multiplications are required with at least one of the complex multiplier modules receiving an output from the input module. Each of the complex multiplier modules receives multiplicands from the at least one multiplicand generator. Furthermore, at least one of the complex multiplier modules receives an output of another complex multiplier module. A map module is provided for receiving outputs of the at least two complex multiplier modules, the map module selecting and applying a multiplication factor to each of the outputs receiv…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.