Multi-channel memory architecture for daisy chained arrangements of nodes with bridging between memory channels
US7334070B2 · kind B2 · utility
27Cited by
8References
30Claims
0Family size
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Key dates
| Filing date | Oct 29, 2004 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Dec 17, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple memory channels of a multi-channel memory architecture are effectively bridged together to enable data traffic associated with various nodes in daisy chain arrangement to be communicated over both memory channels. For example, a daisy chain arrangement of nodes, such as FB-DIMM memory modules disposed in a first memory channel may be coupled to a second memory channel, with support for communicating data associated with one of the nodes over either or both of the first and second memory channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.