Patent · US Expired

Cell builder for different layer stacks

US7334206B2 · kind B2 · utility

4Cited by

23References

20Claims

0Family size

Assignee

LSI Logic Corporation · US

Inventors

Matthias Dinter · Holzkirchen, DE
Juergen Dirks · Holzkirchen, DE
Roland Klemt · Forstern, DE

Key dates

Filing date	Dec 13, 2004
Grant date	Feb 19, 2008
Priority date	—
Expiry date	Jan 30, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/39
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A library cell, a method and/or a system for adding the cell to a circuit is disclosed. The method generally comprises a first step for generating a final layout of the cell having an area of interest in at least one upper layer within a first layer stack used for the circuit, the first layer stack including at most all of a plurality of physical layers available for fabrication. A second step may include placing the final layout in the circuit. A third step may route a network of the circuit through the cell using the at least one upper layer and avoiding the area of interest according to at least one of a plurality of rules.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.