Method and system for generating multiple implementation views of an IC design
US7334209B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2004 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Jul 31, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on an integrated circuit (IC) in which all elements in a row have the same height and all elements in a column have the same width. This array, which may be displayed in a textual or spreadsheet format, forms the high-level placement specification. A software program of this embodiment converts this high-level placement specification into layout and schematic files that can be used by a commercial CAD tool to produce a file for fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.