MOS device for high voltage operation and method of manufacture

US7335543B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• John Chen · Palo Alto, US
• Roger Lee · Boise, US

Key dates

• Filing date: Aug 27, 2004
• Grant date: Feb 26, 2008
• Expiry date: Aug 27, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

A high voltage semiconductor device. The high voltage device has a substrate (e.g., silicon wafer) having a surface region. The substrate has a well region within the substrate and a double diffused drain region within the well region. A gate dielectric layer is overlying the surface region. A gate polysilicon layer is overlying the gate dielectric layer. A mask layer is overlying the gate polysilicon layer. The device also has a gate electrode formed within the gate polysilicon layer. The gate electrode has a first predetermined width and a first predetermined thickness. Preferably, the gate electrode has a first side and a second side formed between the first predetermined width. The gate electrode is coupled to the double diffused drain region within the well region. Preferably, the first side has a lower corner overlying the gate dielectric layer and an upper corner underlying the mask layer and the second side has a lower corner overlying the gate dielectric layer and an upper corner underlying the mask layer. A first insulating region formed from polysilicon is formed at the lower corner on the first side of the gate electrode. The first insulating region extends from the fir…