Control of strain in device layers by prevention of relaxation
US7335545B2 · kind B2 · utility
76Cited by
216References
31Claims
0Family size
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Inventor
Key dates
| Filing date | Sep 15, 2005 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Nov 2, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/938
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.