Method for precision integrated circuit die singulation using differential etch rates
US7335576B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2005 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Nov 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30655
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material. A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate removed to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.