Inventor · Lemon Grove, CA, US

W. Eric Boyd

20Patents
5h-index
22Co-inventors
65Inventor score

Filing activity: Jan 31, 2005 → Aug 29, 2016

Most-cited inventions

PatentTitleAreaCited byStatus
US7235785B2 Imaging device with multiple fields of view incorporating memory-based temperature compensation of an uncooled focal plane array Electricity 137 Expired
US7335576B2 Method for precision integrated circuit die singulation using differential etch rates Electricity 46 Expired
US7649386B2 Field programmable gate array utilizing dedicated memory stacks in a vertical layer format Electricity 7 Active
US7786562B2 Stackable semiconductor chip layer comprising prefabricated trench interconnect vias Electricity 7 Expired
US8271262B1 Portable lip reading sensor system Human Necessities 5 Active
US7902879B2 Field programmable gate array utilizing dedicated memory stacks in a vertical layer format Electricity 4 Active
US8415819B2 Energy harvesting buoy Emerging Cross-Sectional Technologies 3 Active
US8637985B2 Anti-tamper wrapper interconnect method and a device Electricity 2 Active
US8586407B2 Method for depackaging prepackaged integrated circuit die and a product from the method Electricity 1 Active
US7714426B1 Ball grid array package format layers and structure Electricity 1 Active
US7982300B2 Stackable layer containing ball grid array package Electricity 1 Active
US9046322B2 Self-calibrating targeting sight Physics 1 Active
US9728507B2 Cap chip and reroute layer for stacked microelectronic module Electricity 1 Active
US9431275B2 Wire bond through-via structure and method Electricity 1 Active
US7777321B2 Stacked microelectronic layer and module with three-axis channel T-connects Electricity 0 Active
US8609473B2 Method for fabricating a neo-layer using stud bumped bare die Electricity 0 Active
US8637140B2 Method for defining an electrically conductive metal structure on a three-dimensional element and a device made from the method Emerging Cross-Sectional Technologies 0 Active
US8835218B2 Stackable layer containing ball grid array package Electricity 0 Active
US9741680B1 Wire bond through-via structure and method Electricity 0 Active
USRE43877E1 Method for precision integrated circuit die singulation using differential etch rates General 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.