Phase change memory device
US7335906B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2003 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Aug 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A phase change memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having a matrix of memory cells for storing resistance values as data determined by phase change of the cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction of the matrix and word lines each commonly connecting the other ends of plural cells arranged along a second direction of the matrix; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wirings disposed outside of first and second boundaries of a cell layout region in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed outside of one of third and fourth boundaries of the cell layout region in the second direction to connect the word lines to the read/write circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.