Efficient hardware A-buffer using three-dimensional allocation of fragment memory
US7336283B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2002 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Nov 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for arranging fragments in a graphics memory. Each pixel of a display has a corresponding list of fragments in the graphics memory. Each fragment describes a three-dimensional surface at a plurality of sample points associated with the pixel. A predetermined number of fragments are statically allocated to each pixel. Additional space for fragment data is dynamically allocated and deallocated. Each dynamically allocated unit of memory contains fragment data for a plurality of pixels. Fragment data are arranged to exploit modem DRAM capabilities by increasing locality of reference within a single DRAM page, by putting other fragments likely to be referenced soon in pages that belong to non-conflicting banks, and by maintaining bookkeeping structures that allow the relevant DRAM precharge and row activate operations to be scheduled far in advance of access to fragment data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.