Page buffer circuit and method for multi-level NAND programmable memories
US7336538B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2006 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Jul 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell. The enabling means includes reading means for retrieving the existing data value, means for receiving an indication of the target data value, combining means for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication. Conditioning means in the combining mean…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.