PLL with low phase noise non-integer divider
US7336755B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 8, 2004 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Mar 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop with a non-integer divider utilizes a state machine to periodically select a new clock from a plurality of clocks for comparison to a reference signal after division by an integer divide by N block. Based on a desired divider ratio, the state machine selects the new clock that is phase shifted with respect to a presently selected clock. Each change from the presently selected clock to the new clock produces a selected clock cycle that is expanded or contracted by the amount of phase shift between the new clock and the presently selected clock. The integer divide by N block divides the selected clock by the integer portion of the desired divider ratio producing a divided clock that is effectively divided by a non-integer amount.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.