Method and apparatus for caching variable length instructions
US7337272B2 · kind B2 · utility
6Cited by
3References
37Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 1, 2006 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Sep 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction cache controller uses supplemental memory to store a redundant copy of cached instruction data corresponding to a cache boundary position, and thereby enables subsequent single cache access retrieval of an instruction that crosses that boundary position. In one or more embodiments, the cache controller duplicates instruction data for the post-boundary position in the supplemental memory, and multiplexes that copied data into cache data obtained from the pre-boundary position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.