Low fabrication cost, high performance, high reliability chip scale package
US7338890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2005 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | May 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/054
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrie…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.