Integration of pore sealing liner into dual-damascene methods and devices
US7338893B2 · kind B2 · utility
11Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2005 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Apr 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76844
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.