Chip-size package structure and method of the same
US7339279B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 11, 2007 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | May 11, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking and placing the dice on a base and filling a first material layer on the base into a space among the dice on the base. A dielectric layer with first openings is patterned to expose a portion of a conductive line of the dice. A conductive material is filled into the first openings and on the dielectric layer. Subsequently, a second material layer is formed to have a second openings exposing the conductive material and then welding solder balls on the second openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.