Advanced Chip Engineering Technology, Inc.
39Patents
29Active
39Granted
47Portfolio score
Filing activity: Apr 28, 2004 → Nov 10, 2009 · 29 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7238602B2 | Chip-size package structure and method of the same | Electricity | 68 | Expired |
| US7339279B2 | Chip-size package structure and method of the same | Electricity | 58 | Active |
| US8178964B2 | Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same | Electricity | 47 | Active |
| US8178963B2 | Wafer level package with die receiving through-hole and method of the same | Electricity | 43 | Active |
| US7667318B2 | Fan out type wafer level package structure and method of the same | Electricity | 40 | Active |
| US7655501B2 | Wafer level package with good CTE performance | Electricity | 34 | Active |
| US7514767B2 | Fan out type wafer level package structure and method of the same | Electricity | 33 | Active |
| US7061106B2 | Structure of image sensor module and a method for manufacturing of wafer level package | Electricity | 29 | Expired |
| US7812434B2 | Wafer level package with die receiving through-hole and method of the same | Electricity | 27 | Active |
| US7534632B2 | Method for circuits inspection and method of the same | Electricity | 27 | Active |
| US7453148B2 | Structure of dielectric layers in built-up layers of wafer level package | Electricity | 25 | Active |
| US7501310B2 | Structure of image sensor module and method for manufacturing of wafer level package | Electricity | 19 | Active |
| US7557437B2 | Fan out type wafer level package structure and method of the same | Electricity | 17 | Active |
| US7279782B2 | FBGA and COB package structure for image sensor | Electricity | 13 | Expired |
| US7884464B2 | 3D electronic packaging structure having a conductive support substrate | Electricity | 12 | Active |
| US7911044B2 | RF module package for releasing stress | Electricity | 12 | Active |
| US7525185B2 | Semiconductor device package having multi-chips with side-by-side configuration and method of the same | Electricity | 10 | Active |
| US7423335B2 | Sensor module package structure and method of the same | Electricity | 9 | Active |
| US7884461B2 | System-in-package and manufacturing method of the same | Electricity | 8 | Active |
| US7224061B2 | Package structure | Electricity | 8 | Expired |
| US7176567B2 | Semiconductor device protective structure and method for fabricating the same | Electricity | 7 | Expired |
| US7446546B2 | Method and system of trace pull test | Electricity | 7 | Active |
| US7319043B2 | Method and system of trace pull test | Electricity | 7 | Expired |
| US7459729B2 | Semiconductor image device package with die receiving through-hole and method of the same | Electricity | 6 | Active |
| US7342296B2 | Wafer street buffer layer | Electricity | 6 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.