Generating multi-phase clock signals using hierarchical delays
US7339408B2 · kind B2 · utility
13Cited by
33References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 12, 2007 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Jan 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD includes either one or two variable delay lines that provide coarse phase adjustment of an associated input signal. Each HD also includes one or more phase mixers that provide fine phase adjustment of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.