Simulating multiported memories using lower port count memories
US7339592B2 · kind B2 · utility
9Cited by
5References
21Claims
0Family size
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Key dates
| Filing date | Jul 13, 2004 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Mar 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multiple banks. A collector unit coupled to each bank gathers source operands needed to process a program instruction as the source operands output from one or more banks. The collector unit outputs the source operands to an execution unit when all of the source operands needed to process the program instruction have been gathered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.