Non-volatile semiconductor memory device and writing method thereof
US7339827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2005 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Nov 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/511
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.