Providing parallel operand functions using register file and extra path storage
US7340591B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2004 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Mar 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A number of architectural and implementation approaches are described for using extra path (Epath) storage that operate in conjunction with a compute register file to obtain increased instruction level parallelism that more flexibly addresses the requirements of high performance algorithms. A processor that supports a single load data to a register file operation can be doubled in load capability through the use of an extra path storage, an additional independently addressable data memory path, and instruction decode information that specifies two independently load data operations. By allowing the extra path storage to be accessible by arithmetic facilities, the increased data bandwidth can be fully utilized. In addition, flexible approaches to specifying the extra path storage, as a register, as a file, as a stack, as a tightly coupled input/output data interface path, and in conjunction with a scalable register file, can be implemented providing numerous options and capabilities for evolving processor designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.