Method for abstraction of manufacturing test access and control ports to support automated RTL manufacturing test insertion flow for reusable modules
US7340700B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2005 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Feb 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.