Integrated circuit binning and layout design system
US7340710B1 · kind B1 · utility
7Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2005 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | May 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for binning and layout of an integrated circuit design which includes providing a table setting forth predefined widths of signal wires and corresponding spacing to shield wires, characterizing effects on timing, noise, and power distribution based on predefined widths and spacing combinations as functions of the length of the signal wire, and laying out the integrated circuit design based upon the predefined widths of signal wires and corresponding spacing to shield wires. The shield wires are adjacent and on both sides of the routed signal wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.