Stephan Hoerold
5Patents
5h-index
8Co-inventors
48Inventor score
Filing activity: Mar 19, 2001 → Nov 21, 2006
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6665845B1 | System and method for topology based noise estimation of submicron integrated circuit designs | Physics | 58 | Expired |
| US7565638B2 | Density-based layer filler for integrated circuit design | Physics | 26 | Active |
| US6941532B2 | Clock skew verification methodology for grid-based design | Physics | 11 | Expired |
| US7404161B2 | Fullchip functional equivalency and physical verification | Physics | 9 | Expired |
| US7340710B1 | Integrated circuit binning and layout design system | Physics | 7 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.