Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices
US7341905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2004 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Apr 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0109
Abstract
A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material. The sequence consists of sixteen specific mask steps that permit a variety of bipolar/CMOS/DMOS devices to be fabricated. The mask steps include (1) forming at least one N-well in the p-type material, (2) forming an active region, forming a p-type field region, (4) forming a gate oxide, (5) carrying out a p-type implantation, (6) forming polysilicon gate regions, (7) forming a p-base region, (8) forming a N-extended region, (9) forming a p-top region, 10) carrying out an N+ implant, (11) carrying out a P+ implant, (12) forming contacts, (13) depositing a metal layer, (14) forming vias, (15) depositing a metal layer therethrough, and (16) forming a passivation layer. Up to any three of mask steps (4), (7), (8), and (9) may be omitted depending on the type of integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.