Method of manufacturing sidewall spacers on a memory device, and device comprising same

US7341906B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• David K. Hwang · Boise, US
• Kunal R. Parekh · Boise, US
• Michael Willett · Boise, US
• Jigish Trivedi · Boise, US
• Suraj Mathew · Boise, US
• Greg Peterson · Nicholasville, US

Key dates

• Filing date: May 19, 2005
• Grant date: Mar 11, 2008
• Expiry date: Oct 12, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/48

Abstract

The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness …