Single wafer thermal CVD processes for hemispherical grained silicon and nano-crystalline grain-sized polysilicon
US7341907B2 · kind B2 · utility
8Cited by
8References
20Claims
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Key dates
| Filing date | Apr 5, 2005 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Apr 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/662
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Methods for depositing hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are provided. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are deposited in single substrate chemical vapor deposition chambers. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers may be used as electrode layers in semiconductor devices. In one aspect, a two step deposition process is provided to form a nanocrystalline grain-sized polysilicon layer with a reduced roughness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.