Method of manufacturing non-volatile memory
US7341913B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2006 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Jun 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure is lower than that of the mask layer and the isolation structure and the mask layer together form a recession. A spacer is formed at the sidewall of the recession and the recession is filled with an insulating layer. The mask layer and the spacer are removed and a tunneling dielectric layer is formed over the substrate. A first conductive layer is formed to fill the first opening and the isolating layer is removed to form a second opening. A gate dielectric layer and a second conductive layer are formed over the substrate sequentially. The second conductive layer and the first conductive layer are patterned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.