Methods to facilitate etch uniformity and selectivity
US7341941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2005 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Dec 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.