Vertical-type semiconductor device having repetitive-pattern layer
US7342265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2004 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Apr 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/111
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is fabricated to include a withstand-voltage assurance layer designed into a multi-dimensional super junction structure and a group of trench gate electrodes, each of which penetrating a body layer in contact with the multi-dimensional super junction structure to reach the multi-dimensional super junction structure, so that dispersions of an on-resistance of the semiconductor device can be reduced. When a position at which the group of trench gate electrodes is created is shifted in one direction, the size of an overlap area common to the group of trench gate electrodes and an n-type column changes. However, the group of trench gate electrodes is oriented in such a way that the changes in overlap-area size are minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.