Semiconductor metal contamination reduction for ultra-thin gate dielectrics
US7342290B2 · kind B2 · utility
5Cited by
17References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2004 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Jun 10, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.