CMOS circuit arrangement

US7342421B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Jorg Berthold · Munich, DE
• Ralf Brederlow · Poing, DE
• Christian Pacha · Birkenfeld, DE
• Klaus von Arnim · Herzhorn, DE

Key dates

• Filing date: Sep 17, 2004
• Grant date: Mar 11, 2008
• Expiry date: Sep 17, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

In an embodiment of the invention, a CMOS circuit arrangement is provided. The CMOS circuit arrangement includes a PMOS logic circuit providing a logic function, having PMOS field effect transistors, wherein a first operating potential is fed to an input of a PMOS logic circuit, an NMOS logic circuit providing the logic function, having NMOS field effect transistors, a first clock transistor, the first source/drain terminal of which is coupled to an input of the NMOS logic circuit, wherein a clock signal is applied to the gate terminal of the first clock transistor, and wherein a second operating potential is fed to the second source/drain terminal. An output of the PMOS logic circuit and an output of the NMOS logic circuit are coupled to one another. Furthermore, an inverter circuit is coupled to the output of the PMOS logic circuit and to the output of the NMOS logic circuit. At least a portion of the NMOS field effect transistors of the NMOS logic circuit have a first threshold voltage and at least a portion of the PMOS field effect transistors of the PMOS logic circuit have a third threshold voltage. The first clock transistor has a second threshold voltage. The first threshold…