Techniques for sequentially transferring data from a memory device through a parallel interface
US7343470B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2003 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Mar 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address counter. The address counter generates sequential read addresses for the data bits stored in the memory device. The destination circuit generates a clock signal that controls the address counter. The destination circuit can also transmit a start address to the memory device. The address counter sequentially generates a new read address in response to transitions in the clock signal beginning with the start address. Data bits are transferred in parallel from the memory device to the destination circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.