Apparatus and method for reset distribution
US7343569B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2006 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Aug 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A skew-tolerant, glitch-free reset distribution apparatus and method are provided in an intellectual property (IP) block that supports a multi-channel input/output protocol. During reset mode, synchronizers are used to create more predictable timing, to pipeline the propagation delay, and to tolerate RC-induced skews of up to a clock period in routing a reset signal to all the channels and within the channels in an IP block. Two control signals, which are available from programmable logic resource core circuitry, are used to control the input of the reset signal into the IP block. Because the control signals are designed to be glitch-free, the reset signal is therefore also glitch-free, thus preventing the IP block from inadvertently transitioning into or out of reset mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.