Method and system for generating a bitstream view of a design
US7343578B1 · kind B1 · utility
28Cited by
11References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2004 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Oct 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for generating a bitstream view of a programmable logic device (PLD) design are disclosed. The present invention allows for the correlation of a physical circuit description (e.g., one or more of a PLD design's essential configuration bits) and a logical circuit description (e.g., one or more of the logic elements that make up a PLD design), which can also be viewed as correlating one or more of the physical elements of the design's implementation in the PLD with one or more of the design's logical elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.