Method for patterning electrically conducting poly(phenyl acetylene) and poly(diphenyl acetylene)
US7344912B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2005 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | May 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/60
Abstract
Disclosed are methods of fabricating a memory cell structure. More specifically, a copper substrate, including but not limited to copper contacts and/or bit lines, can be formed within a metal-containing layer, for example. Optionally, one or more via openings can then be formed in an overlying dielectric layer to expose one or more of the copper contacts and/or bit lines. Copper sulfide material can be formed thereon. Alternatively, a portion of the exposed copper can be converted to copper sulfide (e.g., Cu2S2 or Cu2S). The copper sulfide material can then be exposed to a vapor phase monomer to facilitate selective growth of a conducting polymer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.